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general description the max1300/max1301 multirange, low-power, 16-bit, successive-approximation, analog-to-digital converters (adcs) operate from a single +5v supply and achieve throughput rates up to 115ksps. a separate digital sup - ply allows digital interfacing with 2.7v to 5.25v systems using the spi-/qspi?-/microwire ? -compatible serial interface. partial power-down mode reduces the supply current to 1.3ma (typ). full power-down mode reduces the power-supply current to 1a (typ). the max1300 provides eight (single-ended) or four (true differential) analog input channels. the max1301 pro - vides four (single-ended) or two (true differential) analog input channels. each analog input channel is indepen - dently software programmable for seven single-ended input ranges [0 to (3 x v ref )/2, (-3 x v ref )/2 to 0, 0 to 3 x v ref , -3 x v ref to 0, (3 x v ref )/4, (3 x v ref )/2, 3 x v ref ] and three differential input ranges [(3 x v ref )/2, 3 x v ref , 6 x v ref ]. an on-chip +4.096v reference offers a small convenient adc solution. the max1300/max1301 also accept an external reference voltage between 3.800v and 4.136v. the max1300 is available in a 24-pin tssop package and the max1301 is available in a 20-pin tssop pack - age. each device is specified for operation from -40c to +85c. applications industrial control systems data-acquisition systems avionics robotics features software-programmable input range for each channel single-ended input ranges (v ref = 4.096v) 0 to (3 x v ref )/2, (-3 x v ref )/2 to 0, 0 to 3 x v ref , -3 x v ref to 0, (3 x v ref )/4, (3 x v ref )/2, 3 x v ref differential input ranges (3 x v ref )/2, 3 x v ref , 6 x v ref eight single-ended or four differential analog inputs (max1300) four single-ended or two differential analog inputs (max1301) 16.5v overvoltage tolerant inputs internal or external reference 115ksps maximum sample rate single +5v power supply 20-/24-pin tssop package pin configurations continued at end of data sheet. 19-3575; rev 3; 12/11 +denotes lead(pb)-free/rohs-compliant package. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. part temp range pin- package channels max1300 aeug+ -40c to +85c 24 tssop 8 max1300beug+ -40c to +85c 24 tssop 8 max1301 aeup+ -40c to +85c 20 tssop 4 max1301beup+ -40c to +85c 20 tssop 4 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 agnd1 agnd2 avdd2 agnd3 ch2 ch1 ch0 avdd1 top view ref refcap dvdd dvdd0 ch6 ch5 ch4 ch3 16 15 14 13 9 10 11 12 dgnd dgndo dout sclk sstrb din cs ch7 tssop max1300 + ordering information pin confgurations evaluation kit available max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs
avdd1 to agnd1 ................................................... -0.3v to +6v avdd2 to agnd2 ................................................... -0.3v to +6v dvdd to dgnd ....................................................... -0.3v to +6v dvddo to dgndo ................................................. -0.3v to +6v dvdd to dvddo .................................................... -0.3v to +6v dvdd, dvddo to avdd1 ....................................... -0.3v to +6v avdd1, dvdd, dvddo to avdd2 ......................... -0.3v to +6v dgnd, dgndo, agnd3, agnd2 to agnd1 ..... -0.3v to +0.3v cs , sclk, din, dout, sstrb to dgndo ......................................... -0.3v to (v dvddo + 0.3v) ch0Cch7 to agnd1 ........................................ -16.5v to +16.5v ref, refcap to agnd1 ................... -0.3v to (v avdd1 + 0.3v) continuous current (any pin) ........................................... 50ma continuous power dissipation (t a = +70c) 20-pin tssop (derate 11mw/c above +70c) ......... 879mw 24-pin tssop (derate 12.2mw/c above +70c) ...... 976mw operating temperature range ........................... -40c to +85c junction temperature ..................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (3 x v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units dc accuracy (notes 1, 2) resolution 16 bits integral nonlinearity inl max130_a 1.0 2 lsb max130_b 1.0 4 differential nonlinearity dnl no missing codes -1 +2 lsb transition noise external or internal reference 1 lsb rms offset error single-ended inputs unipolar 0 20 mv bipolar -1.0 12 differential inputs (note 3) bipolar -2.0 20 channel-to-channel gain matching unipolar or bipolar 0.025 %fsr channel-to-channel offset error matching unipolar or bipolar 1.0 mv offset temperature coeffcient unipolar 3 v/c bipolar 1 fully differential 2 gain error unipolar 0.5 %fsr bipolar 0.8 fully differential 1 gain temperature coeffcient unipolar 2 ppm/c bipolar 1 fully differential 2 dynamic specifications f in(sine-wave) = 5khz, v in = fsr - 0.05db (notes 1, 2) signal-to-noise plus distortion sinad differential inputs, fsr = 6 x v ref 91 db single-ended inputs, fsr = 3 x v ref 89 single-ended inputs, fsr = (3 x v ref )/2 86 single-ended inputs, fsr = (3 x v ref )/4 80 83 maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. electrical characteristics max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (3 x v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units signal-to-noise ratio snr differential inputs, fsr = 6 x v ref 91 db single-ended inputs, fsr = 3 x v ref 89 single-ended inputs, fsr = (3 x v ref )/2 86 single-ended inputs, fsr = (3 x v ref )/4 83 total harmonic distortion (up to the 5th harmonic) thd -97 db spurious-free dynamic range sfdr 92 99 db aperture delay t ad figure 21 15 ns aperture jitter t aj figure 21 100 ps channel-to-channel isolation 105 db conversion rate byte-wide throughput rate f sample external clock mode, figure 2 114 ksps external acquisition mode, figure 3 84 internal clock mode, figure 4 106 analog inputs (ch0Cch3 max1301, ch0Cch7 max1300, agnd1) small-signal bandwidth all input ranges, v in = 100mv p-p (note 2) 2 mhz full-power bandwidth all input ranges, v in = 4v p-p (note 2) 700 khz input voltage range (table 6) v ch_ r[2:1] = 001 (-3 x v ref )/ 4 (+3 x v ref )/ 4 v r[2:1] = 010 (-3 x v ref )/ 2 0 r[2:1] = 011 0 (+3 x v ref )/ 2 r[2:1] = 100 (-3 x v ref )/ 2 (+3 x v ref )/ 2 r[2:1] = 101 -3 x v ref 0 r[2:1] = 110 0 +3 x v ref r[2:1] = 111 -3 x v ref +3 x v ref true-differential analog common- mode voltage range v cmdr dif/ sgl = 1 (note 4) -14 +9 v common-mode rejection ratio cmrr dif/ sgl = 1, input voltage range = (3 x v ref )/4 75 db input current i ch_ -3 x v ref < v ch_ < +3 x v ref -1250 +900 a input capacitance c ch_ 5 pf input resistance r ch_ 17 k? maxim integrated 3 electrical characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (3 x v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units internal reference (bypass refcap with 0.1f to agnd1 and ref with 1.0f to agnd1) reference output voltage v ref 4.056 4.096 4.136 v reference temperature coeffcient tc ref 30 ppm/c reference short-circuit current i refsc ref shorted to agnd1 10 ma ref shorted to avdd -1 reference load regulation i ref = 0 to 0.5ma 0.1 10 mv external reference (refcap = avdd) reference input voltage range v ref 3.800 4.136 v refcap buffer disable threshold v rcth (note 5) v avdd1 - 0.4 v avdd1 - 0.1 v reference input current i ref v ref = +4.096v, external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 90 200 a v ref = +4.096v, full power-down mode 0.1 10 reference input resistance r ref external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 20 45 k? full power-down mode 40 m? digital inputs (din, sclk, cs ) input high voltage v ih 0.7 x v dvddo v input low voltage v il 0.3 x v dvddo v input hysteresis v hyst 0.2 v input leakage current i in v in = 0 to v dvddo -10 +10 a input capacitance c in 10 pf digital outputs (dout, sstrb) output low voltage v ol v dvddo = 4.75v, i sink = 10ma 0.4 v v dvddo = 2.7v, i sink = 5ma 0.4 output high voltage v oh i source = 0.5ma v dvddo - 0.4 v dout tri-state leakage current i ddo cs = v dvddo -10 +10 a power requirements (avdd1 and agnd1, avdd2 and agnd2, dvdd and dgnd, dvddo and dgndo) analog supply voltage avdd1 4.75 5.25 v digital supply voltage dvdd 4.75 5.25 v maxim integrated 4 electrical characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (3 x v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units preamplifer supply voltage avdd2 4.75 5.25 v digital i/o supply voltage dvddo 2.70 5.25 v av dd1 supply current i avdd1 external clock mode, external acquisition mode, or internal clock mode internal reference 3 3.5 ma external reference 2.3 3 dv dd supply current i dvdd external clock mode, external acquisition mode, or internal clock mode 0.8 2 ma av dd2 supply current i avdd2 external clock mode, external acquisition mode, or internal clock mode 13.5 20 ma dv ddo supply current i dvddo external clock mode, external acquisition mode, or internal clock mode 0.01 1 ma total supply current partial power-down mode 1.3 ma full power-down mode 0.5 a power-supply rejection ratio psrr all analog input ranges 0.5 lsb timing characteristics (figures 15 and 16) sclk period t cp external clock mode 0.272 62 s external acquisition mode 0.228 62 internal clock mode 0.1 sclk high pulse width (note 6) t ch external clock mode 109 ns external acquisition mode 92 internal clock mode 40 sclk low pulse width (note 6) t cl external clock mode 109 ns external acquisition mode 92 internal clock mode 40 din to sclk setup t ds 40 ns din to sclk hold t dh 0 ns sclk fall to dout valid t do 40 ns cs fall to dout enable t dv 40 ns maxim integrated 5 electrical characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
note 1: parameter tested at v avdd1 = v avdd2 = v dvdd = v dvddo = 5v. note 2: see definitions in the parameter definitions section at the end of the data sheet. note 3: guaranteed by correlation with single-ended measurements. note 4: not production tested. guaranteed by design. note 5: to ensure external reference operation, v refcap must exceed (v avdd1 - 0.1v). to ensure internal reference operation, v refcap must be below (v avdd1 - 0.4v). bypassing refcap with a 0.1f or larger capacitor to agnd1 sets v refcap 4.096v. the transition point between internal reference mode and external reference mode lies between the refcap buffer disable threshold minimum and maximum values (figures 17 and 18). note 6: the sclk duty cycle can vary between 40% and 60%, as long as the t cl and t ch timing requirements are met. (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (3 x v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) parameter symbol conditions min typ max units cs rise to dout disable t tr 40 ns cs fall to sclk rise setup t css 40 ns cs high minimum pulse width t cspw 40 ns sclk fall to cs rise hold t csh 0 ns sstrb rise to cs fall setup (note 4) 40 ns dout rise/fall time c l = 50pf 10 ns sstrb rise/fall time c l = 50pf 10 ns preamplifier supply current vs. preamplifier supply voltage max1300 toc02 v avdd2 (v) i avdd2 (ma) 5.15 5.05 4.85 4.95 11 12 13 14 16 15 17 18 10 4.75 5.25 external clock mode ain1?ain7 = agnd2 ain0 = +fs t a = +85c t a = +25c t a = -40c digital supply current vs. digital supply voltage max1300 toc03 v dvdd (v) i dvdd (ma) 5.15 5.05 4.95 4.85 0.80 0.85 0.90 0.95 0.75 4.75 5.25 external clock mode data rate = 115ksps t a = +85c t a = +25c t a = -40c analog supply current vs. analog supply voltage max1300 toc01 v avdd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 2.2 2.3 2.4 2.5 2.6 2.1 4.75 5.25 external clock mode t a = +85c t a = +25c t a = -40c maxim integrated 6 electrical characteristics (continued) typical operating characteristics max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) analog supply current vs. analog supply voltage max1300 toc05 v avdd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 0.41 0.42 0.43 0.44 0.45 0.46 0.40 4.75 5.25 t a = +85c t a = +25c t a = -40c partial power-down mode digital supply current vs. digital supply voltage max1300 toc07 v dvdd (v) i dvdd (ma) 5.15 5.05 4.95 4.85 0.111 0.112 0.113 0.114 0.115 0.110 4.75 5.25 t a = +85c t a = +25c t a = -40c partial power-down mode digital i/o supply current vs. digital i/o supply voltage max1300 toc04 v dvddo (v) i dvddo (a) 5.15 5.05 4.95 4.85 17 18 19 20 21 16 4.75 5.25 t a = +85c t a = +25c t a = -40c external clock mode data rate = 115ksps preamplifier supply current vs. preamplifier supply voltage max1300 toc06 v avdd2 (v) i avdd2 (ma) 5.15 5.05 4.95 4.85 0.12 0.14 0.16 0.18 0.20 0.10 4.75 5.25 t a = +85c t a = +25c t a = -40c partial power-down mode ain1 - ain7 = agnd2 ain0 = +fs maxim integrated 7 typical operating characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) note 7: for partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples. partial power-down or full power-down modes were entered thereafter. by using this method, the conversion rate was found by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down or full power-down modes. analog supply current vs. conversion rate max1300 toc09 conversion rate (ksps) i avdd2 (ma) 100 80 60 40 20 13.86 13.87 13.88 13.89 13.90 13.91 13.92 13.93 13.94 13.95 13.85 0 120 continuous external clock mode digital i/o supply current vs. conversion rate max1300 toc11 conversion rate (ksps) i dvddo (ma) 100 80 60 40 20 0.02 0.04 0.06 0.08 0.10 0 0 120 continuous external clock mode analog supply current vs. conversion rate max1300 toc08 conversion rate (ksps) i avdd1 (ma) 100 80 60 40 20 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.32 0 120 continuous external clock mode digital supply current vs. conversion rate max1300 toc10 conversion rate (ksps) i dvdd (ma) 100 80 60 40 20 0.2 0.4 0.6 0.8 1.0 0 0 120 continuous external clock mode maxim integrated 8 typical operating characteristics (continued) www.maximintegrated.com max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) gain drift vs. temperature max1300 toc13 temperature (c) gain error (%fsr) 60 35 10 -15 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 -40 85 3 x v ref bipolar range (3 x v ref )/4 bipolar range common-mode rejection ratio vs. frequency max1300 toc16 frequency (khz) cmrr (db) 1000 100 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 10,000 f sample = 115ksps 3 x v ref bipolar range offset drift vs. temperature max1300 toc14 temperature (c) offset error (mv) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 3 x v ref bipolar range (3 x v ref )/4 bipolar range integral nonlinearity vs. digital output code max1300 toc17 digital output code inl (lsb) 52,428 39,321 13,107 26,214 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 65,535 f sample = 115ksps 3 x v ref bipolar range fft at 5khz max1300 toc19 frequency (khz) magnitude (db) 50 40 30 20 10 -120 -100 -80 -60 -40 -20 0 -140 0 f sample = 115ksps f in(sine wave) = 5khz 3 x v ref bipolar range external reference input current vs. external reference input voltage max1300 toc12 external reference voltage (v) external reference current (a) 4.1 4.0 3.9 77 79 81 83 85 75 3.8 4.2 channel-to-channel isolation vs. input frequency max1300 toc15 frequency (khz) isolation (db) 1000 100 10 -100 -80 -60 -40 -20 0 -120 1 10,000 f sample = 115ksps 3 x v ref bipolar range ch0 to ch2 differential nonlinearity vs. digital output code max1300/01 toc18 digital output code dnl (lsb) 52,428 39,321 13,107 26,214 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 65,535 f sample = 115ksps 3 x v ref bipolar range maxim integrated 9 typical operating characteristics (continued) www.maximintegrated.com max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) snr, sinad, enob vs. sample rate max1300 toc21 sample rate (ksps) snr, sinad (db) 100 10 1 20 40 60 80 100 0 0.1 1000 f in(sine wave) = 5khz 3 x v ref bipolar range enob (bits) 8 10 12 14 16 6 enob snr, sinad -sfdr, thd vs. analog input frequency max1300 toc23 frequency (khz) -sfdr, thd (db) 100 10 -100 -80 -60 -40 -20 0 -120 1 1000 f sample = 115ksps 3 x v ref bipolar range thd -sfdr small-signal bandwidth max1300 toc25 frequency (khz) attenuation (db) 1000 100 10 -40 -35 -30 -25 -20 -15 -10 -5 0 -45 1 10,000 snr, sinad, enob vs. analog input frequency max1300 toc20 frequency (khz) snr, sinad (db) 100 10 10 20 30 40 50 60 70 80 90 100 0 1 1000 enob (bits) 7 8 9 10 11 12 13 14 15 16 6 enob sinad snr f sample = 115ksps 3 x v ref bipolar range -sfdr, thd vs. sample rate max1300 toc22 sample rate (ksps) -sfdr, thd (db) 100 10 1 -100 -80 -60 -40 -20 0 -120 0.1 1000 f in(sine wave) = 5khz 3 x v ref bipolar range thd -sfdr analog input current vs. analog input voltage max1300 toc24 analog input voltage (v) analog input current (ma) (+3 x v ref )/2 0 (-3 x v ref )/2 -0.6 -0.2 0.2 0.6 1.0 -1.0 -3 x v ref +3 x v ref all modes v ref = 4.096v maxim integrated 10 typical operating characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
(v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range, c dout = 50pf, c sstrb = 50pf; unless otherwise noted.) reference voltage vs. time max1300 toc27 1v/div 0v 4ms/div noise histogram (code center) max1300 toc29 code number of hits 32,776 5,000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 0 32,779 65,534 samples 32,777 32,775 32,778 32,780 32,774 full-power bandwidth max1300 toc26 frequency (khz) attenuation (db) 1000 100 10 -40 -35 -30 -25 -20 -15 -10 -5 0 -45 1 10,000 noise histogram (code edge) max1300 toc28 code number of hits 32,787 5,000 10,000 15,000 20,000 25,000 30,000 35,000 0 32,785 32,789 65,534 samples 32,786 32,788 32,790 maxim integrated 11 typical operating characteristics (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
pin name function max1300 max1301 1 2 avdd1 analog supply voltage 1. connect avdd1 to a +4.75v to +5.25v power-supply voltage. bypass avdd1 to agnd1 with a 0.1f capacitor. 2 3 ch0 analog input channel 0 3 4 ch1 analog input channel 1 4 5 ch2 analog input channel 2 5 6 ch3 analog input channel 3 6 ch4 analog input channel 4 7 ch5 analog input channel 5 8 ch6 analog input channel 6 9 ch7 analog input channel 7 10 7 cs active-low chip-select input. when cs is low, data is clocked into the device from din on the rising edge of sclk. with cs low, data is clocked out of dout on the falling edge of sclk. when cs is high, activity on sclk and din is ignored and dout is high impedance. 11 8 din serial data input. when cs is low, data is clocked in on the rising edge of sclk. when cs is high, transitions on din are ignored. 12 9 sstrb serial-strobe output. when using the internal clock, sstrb rising edge transitions indicate that data is ready to be read from the device. when operating in external clock mode, sstrb is always low. sstrb does not tri-state, regardless of the state of cs , and therefore requires a dedicated i/o line. 13 10 sclk serial clock input. when cs is low, transitions on sclk clock data into din and out of dout. when cs is high, transitions on sclk are ignored. 14 11 dout serial data output. when cs is low, data is clocked out of dout with each falling sclk transition. when cs is high, dout is high impedance. 15 12 dgndo digital i/o ground. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 16 13 dgnd digital ground. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 17 14 dvddo digital i/o supply voltage input. connect dvddo to a +2.7v to +5.25v power-supply voltage. bypass dvddo to dgndo with a 0.1f capacitor. 18 15 dvdd digital-supply voltage input. connect dvdd to a +4.75v to +5.25v power-supply voltage. bypass dvdd to dgnd with a 0.1f capacitor. 19 16 refcap bandgap-voltage bypass node. for external reference operation, connect refcap to avdd. for internal reference operation, bypass refcap with a 0.01f capacitor to agnd1 (v refcap 4.096v). 20 17 ref reference-buffer output/adc reference input. for external reference operation, apply an external reference voltage from 3.800v to 4.136v to ref. for internal reference operation, bypassing ref with a 1f capacitor to agnd1 sets v ref = 4.096v 1%. maxim integrated 12 pin description max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
detailed description the max1300/max1301 multirange, low-power, 16-bit successive-approximation adcs operate from a single +5v supply and have a separate digital supply allowing digital interface with 2.7v to 5.25v systems. these 16-bit adcs have internal track-and-hold (t/h) circuitry that sup - ports single-ended and fully differential inputs. for single- ended conversions, the valid analog input voltage range spans from -3 x v ref below ground to +3 x v ref above ground. the maximum allowable differential input voltage spans from -6 x v ref to +6 x v ref . data can be con - verted in a variety of software-programmable channel and data-acquisition configurations. microprocessor (p) con - trol is made easy through an spi-/qspi-/ microwire- compatible serial interface. the max1300 has eight single-ended analog input chan - nels or four differential channels (see the block diagram at the end of the data sheet). the max1301 has four single-ended analog input channels or two differential channels. each analog input channel is independently software programmable for seven single-ended input ranges [0 to (+3 x v ref )/2, (-3 x v ref )/2 to 0, 0 to +3 x v ref , -3 x v ref to 0, (3 x v ref )/4, (3 x v ref )/2, 3 x v ref ] and three differential input ranges [(3 x v ref )/2, 3 x v ref , 6 x v ref ]. additionally, all analog input chan - nels are fault tolerant to 16.5v. a fault condition on an idle channel does not affect the conversion result of other channels. figure 1. typical application circuit pin name function max1300 max1301 21 18 agnd3 analog signal ground 3. agnd3 is the adc negative reference potential. connect agnd3 to agnd1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 22 19 avdd2 analog supply voltage 2. connect avdd2 to a +4.75v to +5.25v power-supply voltage. bypass avdd2 to agnd2 with a 0.1f capacitor. 23 20 agnd2 analog ground 2. this ground carries approximately fve times more current than agnd1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 24 1 agnd1 analog ground 1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 4?20ma plc acceleration pressure temperature wheatestone wheatestone 1f 0.1f agnd2 dgndo agnd3 dgnd avdd2 dvdd avdd1 0.1f 0.1f 0.1f 5.0v 5.0v 5.0v max1300 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 ref agnd1 refcap 0.1f 3.3v mc68hcxx c dvddo sclk cs din sstrb dout v dd sck i/o mosi i/o miso v ss maxim integrated 13 pin description (continued) max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
power supplies to maintain a low-noise environment, the max1300 and max1301 provide separate power supplies for each section of circuitry. table 1 shows the four sepa - rate power supplies. achieve optimal performance using separate avdd1, avdd2, dvdd, and dvddo supplies. alternatively, connect avdd1, avdd2, and dvdd togeth - er as close to the device as possible for a convenient power connection. connect agnd1, agnd2, agnd3, dgnd, and dgndo together as close to the device as possible. bypass each supply to the corresponding ground using a 0.1f capacitor (table 1). if significant low-frequency noise is present, add a 10f capacitor in parallel with the 0.1f bypass capacitor. converter operation the max1300/max1301 adcs feature a fully differen - tial, successive-approximation register (sar) conversion technique and an on-chip t/h block to convert voltage signals into a 16-bit digital result. both singleended and differential configurations are supported with program - mable unipolar and bipolar signal ranges. track-and-hold circuitry the max1300/max1301 feature a switched-capacitor t/h architecture that allows the analog input signal to be stored as charge on sampling capacitors. see figures 2, 3, and 4 for t/h timing and the sampling instants for each operating mode. the max1300/max1301 analog input circuitry buffers the input signal from the sampling capaci - tors, resulting in a constant input impedance with varying input voltage (figure 5). analog input circuitry select differential or single-ended conversions using the associated analog input configuration byte (table 2). the analog input signal source must be capable of driving the adcs 17k input resistance (figure 6). figure 6 shows the simplified analog input circuit. the ana - log inputs are 16.5v fault tolerant and are protected by back-to-back diodes. the summing junction voltage, v sj , is a function of the channels input commonmode voltage: sj cm r1 r1 v 2.375v 1 v r 1 r 2 r 1 r 2 ?? ?? ?? = ++ ?? ?? ?? ++ ?? ?? ?? as a result, the analog input impedance is relatively con - stant over input voltage as shown in figure 5. table 1. max1300/max1301 power supplies and bypassing table 2. analog input configuration byte power supply/ground supply voltage range (v) typical supply current (ma) circuit section bypassing dv ddo / d gndo 2.7 to 5.25 0.03 digital i/o 0.1f to dgndo av dd2 /agnd2 4.75 to 5.25 135 analog circuitry 0.1f to agnd2 av dd1 /agnd1 4.75 to 5.25 3.0 analog circuitry 0.1f to agnd1 dv dd /dgnd 4.75 to 5.25 0.8 digital control logic and memory 0.1f to dgnd bit number name description 7 start start bit. the frst logic 1 after cs goes low defnes the beginning of the analog input confguration byte. 6 c2 channel-select bits. sel[2:0] select the analog input channel to be confgured (t ables 4 and 5). 5 c1 4 c0 3 dif/ sgl differential or single-ended confguration bit. dif/ sgl = 0 confgures the selected analog input channel for single-ended operation. dif/ sgl = 1 confgures the channel for differential operation. in single-ended mode, input voltages are measured between the selected input channel and agnd1, as shown in table 4. in differential mode, the input voltages are measured between two input channels, as shown in table 5. be aware that changing dif/ sgl adjusts the fsr, as shown in table 6. 2 r2 input-range-select bits. r[2:0] select the input voltage range, as shown in table 6 and figure 7. 1 r1 0 r0 maxim integrated 14 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
single-ended conversions are internally referenced to agnd1 (tables 3 and 4). in differential mode, in+ and in- are selected according to tables 3 and 5. when con - figuring differential channels, the differential pair follows the analog configuration byte for the positive channel. for example, to configure ch2 and ch3 for a 3 x v ref differential conversion, set the ch2 analog configuration byte for a differential conversion with the 3 x v ref range (1010 1100). to initiate a conversion for the ch2 and ch3 differential pair, issue the command 1010 0000. analog input bandwidth the max1300/max1301 input-tracking circuitry has a 2mhz small-signal bandwidth. the 2mhz input band - width makes it possible to digitize high-speed transient events. harmonic distortion increases when digitizing signal frequencies above 15khz as shown in the thd and -sfdr vs. input frequency plot in the typical operating characteristics . analog input range and fault tolerance figure 7 illustrates the software-selectable single-ended analog input voltage range that produces a valid digital output. each analog input channel can be independently programmed to one of seven single-ended input ranges by setting the r[2:0] control bits with dif/ sgl = 0. figure 2. external clock-mode conversion (mode 0) high impedance cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din s c2 c1 c0 0 0 0 0 analog input track and hold* dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 byte 4 sstrb hold track hold t acq high impedance *track and hold timing is controlled by sclk. f sample f sclk / 32 sampling instant maxim integrated 15 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
figure 8 illustrates the software-selectable differential analog input voltage range that produces a valid digital output. each analog input differential pair can be inde - pendently programmed to one of three differential input ranges by setting the r[2:0] control bits with dif/ sgl = 1. regardless of the specified input voltage range and whether the channel is selected, each analog input is 16.5v fault tolerant. the analog input fault protection is active whether the device is unpowered or powered. any voltage beyond fsr, but within the 16.5v fault tolerant range, applied to an analog input results in a full-scale output voltage for that channel. clamping diodes with breakdown thresholds in excess of 16.5v protect the max1300/max1301 analog inputs dur - ing esd and other transient events (figure 6). the clamp - ing diodes do not conduct during normal device opera - tion, nor do they limit the current during such transients. when operating in an environment with the potential for high-energy voltage and/or current transients, protect the max1300/max1301 externally. figure 3. external acquisition-mode conversion (mode 1) cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din s c2 c1 c0 0 0 0 0 analog input track and hold* hold dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 byte 4 sstrb intclk** 1 2 3 14 15 16 17 track hold t acq 100ns to 400ns f intclk 4.5mhz f sample f sclk / 32 + f intclk / 17 *track and hold timing is controlled by sclk. **intclk is an internal signal and is not accessible to the user. sampling instant high impedance maxim integrated 16 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
figure 4. internal clock-mode conversion (mode 2) figure 5. analog input current vs. input voltage figure 6. simplified analog input circuit cs sclk 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 din s c2 c1 c0 0 0 0 0 analog input track and hold* track dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 sstrb intclk** 1 2 3 25 26 27 28 9 10 11 12 13 14 15 16 10 11 12 13 14 hold hold t acq 100ns to 400ns f intclk 4.5mhz f sample f sclk / 24 + f intclk / 28 *track and hold timing is controlled by intclk, and is not accessible to the user. **intclk is an internal signal and is not accessible to the user. sampling instant high impedance analog input voltage (v) analog input current (ma) 0 -0.6 -0.2 0.2 0.6 1.0 -1.0 all modes (+3 x v ref )/2 (-3 x v ref )/2 -3 x v ref +3 x v ref max1300 max1301 r2 r1 v sj *r source analog signal source r2 r1 v sj *r source analog signal source in_+ in_+ *minimize r source to avoid gain error and distortion. maxim integrated 17 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
differential common-mode range the max1300/max1301 differential common-mode range (v cmdr ) must remain within -14v to +10v to obtain valid conversion results. the differential common-mode range is defined as: ( ) ( ) cmdr ch_ ch_ v 2 ? ++ = in addition to the common-mode input voltage limitations, each individual analog input must be limited to 16.5v with respect to agnd1. the range-select bits r[2:0] in the analog input con - figuration bytes determine the full-scale range for the corresponding channel (tables 2 and 6). figures 9, 10, and 11 show the valid analog input voltage ranges for the max1300/max1301 when operating with fsr = (3 x v ref )/2, fsr = 3 x v ref , and fsr = 6 x v ref , respectively. the shaded area contains the valid com - mon-mode voltage ranges that support the entire fsr. table 3. input data word formats table 4. channel selection in single-ended mode (dif/ sgl = 0) table 5. channel selection in true-differential mode (dif/ sgl = 1) operation data bit d7 (start) d6 d5 d4 d3 d2 d1 d0 conversion-start byte (tables 4 and 5) 1 c2 c1 c0 0 0 0 0 analog-input confguration byte (table 2) 1 c2 c1 c0 dif/ sgl r2 r1 r0 mode-control byte (table 7) 1 m2 m1 m0 1 0 0 0 channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 0 0 0 + - 0 0 1 + - 0 1 0 + - 0 1 1 + - 1 0 0 + - 1 0 1 + - 1 1 0 + - 1 1 1 + - channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 0 0 0 + - 0 0 1 reserved 0 1 0 + - 0 1 1 reserved 1 0 0 + - 1 0 1 reserved 1 1 0 + - 1 1 1 reserved maxim integrated g 18 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
digital interface the max1300/max1301 feature a serial interface that is compatible with spi/qspi and microwire devices. din, dout, sclk, cs , and sstrb facilitate bidirectional communication between the max1300/max1301 and the master at sclk rates up to 10mhz (internal clock mode, mode 2), 3.67mhz (external clock mode, mode 0), or 4.39mhz (external acquisition mode, mode 1). the master, typically a microcontroller, should use the cpol = 0, cpha = 0, spi transfer format, as shown in the timing diagrams of figures 2, 3, and 4. the digital interface is used to: ? select single-ended or true-differential input channel configurations ? select the unipolar or bipolar input range ? select the mode of operation: external clock (mode 0) external acquisition (mode 1) internal clock (mode 2) reset (mode 4) partial power-down (mode 6) full power-down (mode 7) ? initiate conversions and read results chip select ( cs ) cs enables communication with the max1300/max1301. when cs is low, data is clocked into the device from din on the rising edge of sclk and data is clocked out of dout on the falling edge of sclk. when cs is high, activity on sclk and din is ignored and dout is high impedance allowing dout to be shared with other periph - erals. sstrb is never high impedance and therefore can - not be shared with other peripherals. serial strobe output (sstrb) as shown in figures 3 and 4, the sstrb transitions high to indicate that the adc has completed a conversion and results are ready to be read by the master. sstrb remains low in the external clock mode (figure 2) and consequently may be left unconnected. sstrb is driven high or low regardless of the state of cs , therefore sstrb cannot be shared with other peripherals. figure 7. single-ended input voltage ranges figure 8. differential input voltage ranges 001 010 011 100 101 110 111 0 (-3 x v ref )/2 -3 x v ref +3 x v ref (+3 x v ref )/2 each input is fault tolerant to 16.5v. v ref = 4.096v. (ch_) - agnd1 (v) input range selection bits, r[2:0] fsr = (3 x v ref )/2 fsr = 6v fsr = (3 x v ref )/2 fsr = 3 x v ref fsr = 3 x v ref fsr = 3 x v ref fsr = 6 x v ref 001 010 011 100 101 110 111 -3 x v ref -6 x v ref +6 x v ref +3 x v ref each input is fault tolerant to 16.5v. v ref = 4.096v. (ch_+) - (ch_-) (v) input range selection bits, r[2:0] 0 fsr = 3 x v ref fsr = 6 x v ref fsr = 12 x v ref maxim integrated 19 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
table 6. range-select bits *conversion-start byte (see table 3). **mode-control byte (see table 3). dif/ sgl r2 r1 r0 mode transfer function 0 0 0 0 no range change* 0 0 0 1 single-ended bipolar (-3 x v ref )/4 to (+3 x v ref )/4 full-scale range (fsr) = (3 x v ref )/2 figure 12 0 0 1 0 single-ended unipolar (-3 x v ref )/2 to 0 fsr = (3 x v ref )/2 figure 13 0 0 1 1 single-ended unipolar 0 to (+3 x v ref )/2 fsr = (+3 x v ref )/2 figure 14 0 1 0 0 single-ended bipolar (-3 x v ref )/2 to (+3 x v ref )/2 fsr = 3 x v ref figure 12 0 1 0 1 single-ended unipolar -3 x v ref to 0 fsr = 3 x v ref figure 13 0 1 1 0 single-ended unipolar 0 to +3 x v ref fsr = 3 x v ref figure 14 0 1 1 1 default setting single-ended bipolar -3 x v ref to +3 x v ref fsr = 6 x v ref figure 12 1 0 0 0 no range change** 1 0 0 1 differential bipolar (-3 x v ref )/2 to (+3 x v ref )/2 fsr = 3 x v ref figure 12 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 differential bipolar -3 x v ref to +3 x v ref fsr = 6 x v ref figure 12 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 differential bipolar -6 x v ref to +6 x v ref fsr = 12 x v ref figure 12 maxim integrated 20 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
start bit communication with the max1300/max1301 is accom - plished using the three input data word formats shown in table 3. each input data word begins with a start bit. the start bit is defined as the first high bit clocked into din with cs low when any of the following are true: ? data conversion is not in process and all data from the previous conversion has clocked out of dout. ? the device is configured for operation in external clock mode (mode 0) and previous conversion-result bits b15Cb3 have clocked out of dout. ? the device is configured for operation in external acquisition mode (mode 1) and previous conversion - result bits b15Cb7 have clocked out of dout. ? the device is configured for operation in internal clock mode, (mode 2) and previous conversionresult bits b15Cb4 have clocked out of dout. output data format output data is clocked out of dout in offset binary format on the falling edge of sclk, msb first (b15). for output binary codes, see the transfer function section and figures 12, 13, and 14. confguring analog inputs each analog input has two configurable parameters: ? single-ended or true-differential input ? input voltage range these parameters are configured using the analog input configuration byte as shown in table 2. each analog input has a dedicated register to store its input configuration information. the timing diagram of figure 15 shows how to write to the analog input configuration registers. figure 16 shows dout and sstrb timing. transfer function an adcs transfer function defines the relationship between the analog input voltage and the digital out - put code. figures 12, 13, and 14 show the max1300/ max1301 transfer functions. the transfer function is determined by the following characteristics: ? analog input voltage range ? single-ended or differential configuration ? reference voltage the axes of an adc transfer function are typically in least significant bits (lsbs). for the max1300/max1301, an lsb is calculated using the following equation: ref n fsr v 1 l s b 2 4.096v = where n is the number of bits (n = 16) and fsr is the full-scale range (see figures 7 and 8). figure 9. common-mode voltage vs. input voltage (fsr = 3 x v ref ) figure 11. common-mode voltage vs. input voltage (fsr = 12 x v ref ) figure 10. common-mode voltage vs. input voltage (fsr = 6 x v ref ) input voltage (v) common-mode voltage (v) 12 6 0 -6 -12 -12 -8 -4 0 4 8 12 -16 -18 18 input voltage (v) common-mode voltage (v) 12 6 0 -6 -12 -12 -8 -4 0 4 8 12 -16 -18 18 input voltage (v) common-mode voltage (v) 12 6 0 -6 -12 -12 -8 -4 0 4 8 12 -16 -18 18 maxim integrated g 21 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
mode control the max1300/max1301 contain one byte-wide mode - control register. the timing diagram of figure 15 shows how to use the mode-control byte, and the mode-control byte format is shown in table 7. the mode-control byte is used to select the conversion method and to control the power modes of the max1300/max1301. selecting the conversion method the conversion method is selected using the mode-con - trol byte (see the mode control section), and the conver - sion is initiated using a conversion-start command (table 3, and figures 2, 3, and 4).the max1300/max1301 convert analog signals to digital data using one of three methods: ? external clock mode, mode 0 (figure 2) ? highest maximum throughput (see the electrical characteristics table) ? user controls the sample instant ? cs remains low during the conversion ? user supplies sclk throughout the adc conversion and reads data at dout ? external acquisition mode, mode 1 (figure 3) ? lowest maximum throughput (see the electrical characteristics table) ? user controls the sample instant ? user supplies two bytes of sclk, then drives cs high to relieve processor load while the adc converts ? after sstrb transitions high, the user supplies two bytes of sclk and reads data at dout ? internal clock mode, mode 2 (figure 4) ? high maximum throughput (see the electrical characteristics table) figure 12. ideal bipolar transfer function, single-ended or differential input figure 14. ideal unipolar transfer function, single-ended input, 0 to +fsr figure 13. ideal unipolar transfer function, single-ended input, -fsr to 0 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr -32,768 -32,766 0 +32,765 +32,767 input voltage (lsb [decimal]) agnd1 (dif/sgl = 0) ov (dif/sgl = 1) fsr -1 +1 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr 0 1 2 3 32,768 65,533 65,535 input voltage (lsb [decimal]) (agnd1) fsr 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr 0 1 2 3 32,768 65,533 65,535 input voltage (lsb [decimal]) (agnd1) fsr maxim integrated 22 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
? the internal clock controls the sampling instant ? user supplies one byte of sclk, then drives cs high to relieve processor load while the adc converts ? after sstrb transitions high, the user supplies two bytes of sclk and reads data at dout external clock mode (mode 0) the max1300/max1301s fastest maximum throughput rate is achieved operating in external clock mode. sclk controls both the acquisition and conversion of the analog signal, facilitating precise control over when the analog signal is captured. the analog input sampling instant is at the falling edge of the 14th sclk (figure 2). since sclk drives the conversion in external clock mode, the sclk frequency should remain constant while the conversion is clocked. the minimum sclk frequency prevents droop in the internal sampling capacitor voltages during conversion. sstrb remains low in the external clock mode, and as a result may be left unconnected if the max1300/ max1301 will always be used in the external clock mode. figure 15. analog input configuration byte and mode-control byte timing figure 16. dout and sstrb timing table 7. mode-control byte bit number bit name description 7 start start bit. the frst logic 1 after cs goes low defnes the beginning of the mode-control byte. 6 m2 mode-control bits. m[2:0] select the mode of operation as shown in table 8. 5 m1 4 m0 3 1 bit 3 must be a logic 1 for the mode-control byte. 2 0 bit 2 must be a logic 0 for the mode-control byte. 1 0 bit 1 must be a logic 0 for the mode-control byte. 0 0 bit 0 must be a logic 0 for the mode-control byte. cs sclk din dout 1 8 start sel2 sel1 sel0 r2 r1 r0 dif/sgl t cl t cp t ch t dv t css t ds t dh t csh t cspw t tr 1 8 start m2 m1 m0 1 0 0 0 analog input configuration byte mode control byte high impedance high impedance high impedance cs sclk dout t css sstrb t sscs msb t do note: sstrb and cs remain low in external clock mode (mode 0). high impedance maxim integrated 23 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
external acquisition mode (mode 1) the slowest maximum throughput rate is achieved with the external acquisition method. sclk controls the acqui - sition of the analog signal in external acquisition mode, facilitating precise control over when the analog signal is captured. the internal clock controls the conversion of the analog input voltage. the analog input sampling instant is at the falling edge of the 16th sclk (figure 3). for the external acquisition mode, cs must remain low for the first 15 clock cycles and the rise on or after the falling edge of the 16th sclk cycle as shown in figure 3. for optimal performance, idle din and sclk during the conversion. with careful board layout, transitions at din and sclk during the conversion have a minimal impact on the conversion result. after the conversion is complete, sstrb asserts high and cs can be brought low to read the conversion result. sstrb returns low on the rising sclk edge of the sub - sequent start bit. internal clock mode (mode 2) in internal clock mode, the internal clock controls both acquisition and conversion of the analog signal. the inter - nal clock starts approximately 100ns to 400ns after the falling edge of the eighth sclk and has a rate of about 4.5mhz. the analog input sampling instant occurs at the falling edge of the 11th internal clock signal (figure 4). for the internal clock mode, cs must remain low for the first seven sclk cycles and then rise on or after the fall - ing edge of the eighth sclk cycle. after the conversion is complete, sstrb asserts high and cs can be brought low to read the conversion result. sstrb returns low on the rising sclk edge of the subsequent start bit. reset (mode 4) as shown in table 8, set m[2:0] = 100 to reset the max1300/max1301 to its default conditions. the default conditions are full power operation with each channel configured for 3 x v ref , bipolar, single-ended conver - sions using external clock mode (mode 0). partial power-down mode (mode 6) as shown in table 8, when m[2:0] = 110, the device enters partial power-down mode. in partial powerdown, all ana - log portions of the device are powered down except for the reference voltage generator and bias supplies. to exit partial power-down, change the mode by issuing one of the following mode-control bytes (see the mode control section): ? external-clock-mode control byte ? external-acquisition-mode control byte ? internal-clock-mode control byte ? reset byte ? full power-down-mode control byte this prevents the max1300/max1301 from inadvertently exiting partial power-down mode because of a cs glitch in a noisy digital environment. full power-down mode (mode 7) when m[2:0] = 111, the device enters full power-down mode and the total supply current falls to 1a (typ). in full power-down, all analog portions of the device are powered down. when using the internal reference, upon exiting full power-down mode, allow 10ms for the internal reference voltage to stabilize prior to initiating a conversion. to exit full power-down, change the mode by issuing one of the following mode-control bytes (see the mode control section ): ? external-clock-mode control byte table 8. mode-control bits m[2:0] m2 m1 m0 mode 0 0 0 external clock (default) 0 0 1 external acquisition 0 1 0 internal clock 0 1 1 reserved 1 0 0 reset 1 0 1 reserved 1 1 0 partial power-down 1 1 1 full power-down maxim integrated 24 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
? external-acquisition-mode control byte ? internal-clock-mode control byte ? reset byte ? partial power-down-mode control byte this prevents the max1300/max1301 from inadvertently exiting full power-down mode because of a cs glitch in a noisy digital environment. power-on reset the max1300/max1301 power up in normal operation configured for external clock mode with all circuitry active (tables 7 and 8). each analog input channel (ch0Cch7) is set for single-ended conversions with a 3 x v ref bipolar input range (table 6). allow the power supplies to stabilize after power-up. do not initiate any conversions until the power supplies have sta - bilized. additionally, allow 10ms for the internal reference to stabilize when c ref = 1.0f and c refcap = 0.1f. larger reference capacitors require longer stabilization times. internal or external reference the max1300/max1301 operate with either an internal or external reference. the reference voltage impacts the adcs fsr (figures 12, 13, and 14). an external refer - ence is recommended if more accuracy is required than the internal reference provides, and/or multiple converters require the same reference voltage. internal reference the max1300/max1301 contain an internal 4.096v bandgap reference. this bandgap reference is connected to refcap through a nominal 5k resistor (figure 17). the voltage at refcap is buffered creating 4.096v at ref. when using the internal reference, bypass refcap with a 0.1f or greater capacitor to agnd1 and bypass ref with a 1.0f or greater capacitor to agnd1. external reference for external reference operation, disable the internal reference and reference buffer by connecting refcap to avdd1. with avdd1 connected to refcap, ref becomes a high-impedance input and accepts an external reference voltage. the max1300/max1301 can accept an external reference voltage of 4.096v or less. however, to meet all of the electrical characteristic specifications, v ref must be > 38v. the max1300/ max1301 external reference current varies depending on the applied refer - ence voltage and the operating mode (see the external reference input current vs. external reference input voltage in the typical operating characteristics ). applications information noise reduction additional samples can be taken and averaged (oversam - pling) to remove the effect of transition noise on conver - sion results. the square root of the number of samples determines the improvement in performance. for example, with 2/3lsb rms (4lsb p-p ) transition noise, 16 (4 2 = 16) samples must be taken to reduce the noise to 1lsb p-p . interface with 0 to 10v signals in industrial control applications, 0 to 10v signaling is common. for 0 to 10v applications, configure the selected max1300/max1301 input channel for the single-ended 0 to 3 x v ref input range (r[2:0] = 110, table 6). the 0 to 3 x v ref range accommodates 0 to 10v where the signals saturate at approximately 3 x v ref if out of range. interface with 4C20ma signals figure 19 illustrates a simple interface between the max1300/max1301 and a 4C20ma signal. 4C20ma sig - naling can be used as a binary switch (4ma represents a logic-low signal, 20ma represents a logic-high signal), or for precision communication where currents between 4ma and 20ma represent intermediate analog data. for binary switch applications, connect the 4C20ma signal to the max1300/max1301 with a resistor to ground. for example, a 250 resistor converts the 4C20ma signal to a 1v to 5v signal. adjust the resistor value so the parallel combination of the resistor and the max1300/max1301 source impedance is 250. in this application, select the single-ended 0 to (3 x v ref )/2 range (r[2:0] = 011, table 6). for applications that require precision measurements of continuous analog currents between 4ma and 20ma, use a buffer to prevent the max1300/max1301 input from diverting current from the 4C20ma signal. figure 17. internal reference operation ref refcap agnd1 4.096v bandgap reference 5k? 1x sar adc ref 4.096v 1.0f 0.1f v rcth max1300 max1301 maxim integrated 25 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
bridge application the max1300/max1301 convert 1khz signals more accurately than a similar sigma-delta converter that might be considered in bridge applications. the input impedance of the max1300, in combination with the current-limiting resistors, can affect the gain of the max1300. in many applications this error is acceptable, but for applications that cannot tolerate this error, the max1300 inputs can be buffered (figure 20). connect the bridge to a low-offset differential amplifier and then the true-differential inputs of the max1300/max1301. larger excitation voltages take advantage of more of the (3 x v ref )/4 differential input voltage range. select an input voltage range that matches the amplifier output. be aware of the amplifier offset and offset-drift errors when selecting an appropriate amplifier. dynamically adjusting the input range software control of each channels analog input range and the unipolar endpoint overlap specification make it possible for the user to change the input range for a chan - nel dynamically and improve performance in some appli - cations. changing the input range results in a small lsb step-size over a wider output voltage range. for example, by switching between a (-3 x v ref )/2 to 0v range and a 0 to (+3 x v ref )/2 range, an lsb is ref ref ( 3 v )/2 v 65,536 4.096 + but the input voltage range effectively spans from (-3 x v ref )/2 to (+3 x v ref )/2 (fsr = 3 x v ref ). layout, grounding, and bypassing careful pc board layout is essential for best system performance. boards should have separate analog and digital ground planes and ensure that digital and analog signals are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. figure 1 shows the recommended system ground con - nections. establish an analog ground point at agnd1 and a digital ground point at dgnd. connect all analog grounds to the star analog ground. connect the digital grounds to the star digital ground. connect the digital ground plane to the analog ground plane at one point. for lowest noise operation, make the ground return to the star grounds power-supply low impedance and as short as possible. high-frequency noise in the avdd1 power supply degrades the adcs high-speed comparator performance. bypass avdd1 to agnd1 with a 0.1f ceramic surface- mount capacitor. make bypass capacitor connections as short as possible. 3dudphwhuhqlwlrqv integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. the max1300/max1301 inl is measured using the endpoint method. figure 18. external reference operation ref refcap agnd1 4.096v bandgap reference 5k? 1x sar adc ref 4.096v 1.0f v rcth max1300 max1301 av dd1 max6341 v+ 1.0f out gnd in maxim integrated 26 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of greater than -1 lsb guarantees no missing codes and a monotonic transfer function. transition noise transition noise is the amount of noise that appears at a code transition on the adc transfer function. conversions performed with the analog input right at the code transi - tion can result in code flickering in the lsbs. channel-to-channel isolation channel-to-channel isolation indicates how well each analog input is isolated from the others. the channel- tochannel isolation for these devices is measured by applying a near full-scale magnitude 5khz sine wave to the selected analog input channel while applying an equal magnitude sine wave of a different frequency to all unselected channels. an fft of the selected channel out - put is used to determine the ratio of the magnitudes of the signal applied to the unselected channels and the 5khz signal applied to the selected analog input channel. this ratio is reported, in db, as channelto-channel isolation. figure 19. 4C20ma application figure 20. bridge application max1300 250? 4?20ma input 250? 4?20ma input ch0 ch8 c max1300 max1301 ch0 ref p ch1 low-offset differential amplifier bridge maxim integrated 27 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
unipolar offset error -fsr to 0v when a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0xffff). ideally, the transition from 0xffff to 0xfffe occurs at agnd1 - 0.5 lsb. unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. 0v to +fsr when a zero-scale analog input voltage is applied to the converter inputs, the digital output is all zeros (0x0000). ideally, the transition from 0x0000 to 0x0001 occurs at agnd1 + 0.5 lsb. unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. bipolar offset error when a zero-scale analog input voltage is applied to the converter inputs, the digital output is a one followed by all zeros (0x8000). ideally, the transition from 0x7fff to 0x8000 occurs at (2 n-1 - 0.5)lsb. bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point, with untested channels grounded. gain error when a positive full-scale voltage is applied to the con - verter inputs, the digital output is all ones (0xffff). the transition from 0xfffe to 0xffff occurs at 1.5 lsb below full scale. gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed and all untested channels grounded. unipolar endpoint overlap unipolar endpoint overlap is the change in offset when switching between complementary input voltage ranges. for example, the difference between the voltage that results in a 0xffff output in the -3 x v ref /2 to 0v input voltage range and the voltage that results in a 0x0000 output in the 0 to +3 x v ref /2 input voltage range is the unipolar endpoint overlap. the unipolar endpoint overlap is positive for the max1300/max1301, preventing loss of signal or a dead zone when switching between adjacent analog input voltage ranges. small-signal bandwidth a 100mv p-p sine wave is applied to the adc, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. full-power bandwidth a 95% of full-scale sine wave is applied to the adc, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. common-mode rejection ratio (cmrr) cmrr is the ability of a device to reject a signal that is common to or applied to both input terminals. the com - mon-mode signal can be either an ac or a dc signal or a combination of the two. cmr is expressed in decibels. common-mode rejection ratio is the ratio of the differen - tial signal gain to the common-mode signal gain. cmrr applies only to differential operation. power-supply rejection ratio (psrr) psrr is the ratio of the output-voltage shift to the power-supply-voltage shift for a fixed input voltage. for the max1300/max1301, av dd1 can vary from 4.75v to 5.25v. psrr is expressed in decibels and is calculated using the following equation: out out 5.25v 4.75v psrr[db] 20 log v (5.25v) v (4.75v) ? ? ?? = ?? ?? for the max1300/max1301, psrr is tested in bipolar operation with the analog inputs grounded. aperture jitter aperture jitter, t aj , is the statistical distribution of the variation in the sampling instant (figure 21). aperture delay aperture delay, t ad , is the time from the falling edge of sclk to the sampling instant (figure 21). signal-to-noise ratio (snr) snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral compo - nents to the nyquist frequency excluding the fundamen - tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus dis - tortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. rms rms signal sinad(db) 20 log noise ?? = ?? ?? maxim integrated 28 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. with an input range equal to the adcs full-scale range, calculate the enob as follows: sinad 1.76 enob 6.02 ? ?? = ?? ?? total harmonic distortion (thd) for the max1300/max1301, thd is the ratio of the rms sum of the input signals first four harmonic components to the fundamental itself. this is expressed as: 2222 2345 1 v v v v thd 20 log v ?? +++ ?? = ?? ?? ?? where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonic components. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest spectral component. figure 21. aperture diagram t ad t aj intclk (mode 2) analog input track and hold track hold sample instant sclk (mode 0) 13 14 15 sclk (mode 1) 15 16 10 11 12 maxim integrated 29 max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
package type package code outline no. land pattern no. 20 tssop u20+2 21-0066 90-0116 24 tssop u24+1 90-0118 max1300 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 analog input mux and multirange circuitry pga agnd2 av dd2 4.096v bandgap reference 1x 5k? in ref refcap ref control logic and registers fifo clock out sar adc serial i/o agnd2 avdd2 agnd3 avdd1 dgnd dvdd dgndo sclk dout sstrb din cs dvddo 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 agnd2 avdd2 agnd3 ref ch1 ch0 avdd1 agnd1 refcap dvdd dvddo dgnd din cs ch3 ch2 12 11 9 10 dgndo dout sclk sstrb max1301 tssop top view maxim integrated 30 block diagram 3lqrqjxudwlrqvfrqwlqxhg package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs www.maximintegrated.com
revision number revision date description pages changed 0 11/06 initial release 1 2 6/10 updated electrical characteristics tables, tocs to optimize yield. 1C10, 13, 14, 15, 17C21, 24, 25, 26, 28, 31 3 12/11 released max1300 and updated the electrical characteristics table. 1, 2 ? 2011 maxim integrated products, inc. 31 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max1300/max1301 8- and 4-channel, 3 x v ref multirange inputs, serial 16-bit adcs for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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